DESIGN, DEVELOP, AND INTEGRATION OF DMA CONTROLLER FOR OPEN-POWER BASED PROCESSOR SOC

MODULE

Design of the DMA controller and integration of that with the open-power-based processor SoC.

ROLE

The direct Memory Access (DMA) technique provides direct access to the peripherals and memory while the processor is temporarily disabled or busy with executing some other commands in parallel. DMA gets control of the buses to transfer the data directly to the I/O devices. DMA completes the data transfer to all peripherals without the interference of the processor.  

The DMA controller supports 8 channels with 32 – bit data transfer and it has an interface towards user logic for data read and write. The channel assignment is done based on priority.

 This project proposes to design, develop and integrate DMA controller for Open-Power processor A2O core-based fabless SoC through AXI4 interface. The methodology used for designing is: Design State Machines, Develop Verilog HDL code, Simulate using ModelSim Questa® and Synthesis using Vivado design suite-Xilinx®.

GENERAL BLOCK DIAGRAM

DMA DESIGN PROPOSED MODEL

This DMA consists of a total of 8 channels which are used for the data transfer mechanism based on the request given by the particular peripheral. The given request is checked after asserted by the peripheral whether it is valid or not with the help of the Control and Status register which is present in every individual channel.

Channel priority and Channel priority Arbitration are the important blocks that give a valid response to the DMA engine for the further transaction of data along with the specified address.

In this design, two interfaces are provided for the handshake purpose. Pointers are used for the interconnection between the interfaces.

AXI4 bus interface is used to interconnect the modules which are present in this SoC.